1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a lead frame and a semiconductor package with such lead frame.
2. Background of the Related Art
Generally, a lead frame is a metal structure for use in packaging a semiconductor chip. The lead frame is usually made of copper alloy.
FIG. 1 is a diagram showing plane view of a related art quad flat package (QFP) type lead frame. As shown in FIG. 1, a lead frame 21a includes a guide rail 34, a die pad 24, a plurality of inner leads 26 and a plurality of outer leads 27. The guide rail 34 is formed at lower and upper sides of the lead frame 21a to support the overall lead frame structure and guides the lead frame 21a during feeding. The die pad 24 (i.e., a paddle) is formed at the center of the lead frame 21a for mounting a semiconductor chip 23. The die pad 24 is connected to tie bars 22a to be supported by the tie bars 22a, and the die pad 24 is lower than the other portions of the lead frame 21a. The tie bars 22a are extended from edges, for example corners, of the lead frame 21a.
In other words, some portions of the tie bars 22a are bent with a predetermined slope to allow the die pad 24 to be more down-set than the inner leads 26. A gap is formed between the die pad 24 and the inner leads 26. Front ends of the inner leads 26 are disposed around the die pad 24. The outer leads 27 are formed at opposite ends of the inner leads 26 to respectively correspond to the inner leads 26.
A dam bar 28 is formed between the corresponding inner and outer leads 26 and 27. The dam bar 28 is molded by an epoxy molding compound EMC) and then removed during trimming.
The process for making a package with the lead frame 21a will now be described. Dicing of chips on a wafer is performed after a fabrication process for forming an integrated circuit on the wafer. Chip bonding is then performed to mount the chips on the die pad 24 of the lead frame. Wire bonding is performed to electrically connect a bonding pad 25 on the chip 23 with the inner lead 26 of the lead frame 21a using a gold wire 30. Then, molding is performed to shield the chip 23 and the gold wire 30.
After the molding process, trimming is performed to cut the tie bars 22a and the dam bar 28 of the lead frame 21a. Then, forming is performed to form the outer leads 27 to a predetermined form, and soldering is performed. Thus, a semiconductor package as shown in FIG. 2 can be obtained.
However, the related art lead frame 21a has problems in that a lead frame depends on the size of a chip. In other words, when the size of a chip is larger than the die pad, a lead frame having a new die pad corresponding to the size of the chip is designed and fabricated.
Since the die pad 24 is down-set to be disposed lower than the inner lead 26, tips of the inner leads 26 prevent the chip from being mounted on the die pad 24 if the chip 23 is larger than the tip area between the inner leads 26. In addition, the edges of the chip 23 can shield the bonding area of the inner lead 26 to prevent wire bonding. Thus, the size of the chip can only be changed within the range that the chip 23 does not contact with the tip of the inner lead 26 as shown in a dotted line of FIG. 2. Accordingly, it is difficult to use chips having various sizes within the lead frame 1a.
FIGS. 3 and 4 show related art padless lead frame disclosed in U.S. Pat. No. 5,554,886. In FIGS. 3 and 4, edges of a chip 23 are disposed on the inner leads 26.
However, the related art padless lead frame is for a dual in-line package type lead frame 31b and has problems because it is difficult or impossible to fabricate a high pin count package such as the QFP type lead frame 21a. Further, since the lead frame 31b has no die pad, it is difficult or impossible to mount a chip that is smaller than an inner area of inner leads 36. In other words, the related art padless lead frame 31b can be used only to package a chip that is larger than the tip of the inner leads 36 and is not applicable to package a chip smaller than the tip of the inner leads 36. In addition, in the package process, the related art padless lead frame has a problem that lead frames having various sizes should separately be provided depending on the size of the chip to allow distances between the inner leads 36 to be different.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.